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sequential circuit

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sequential circuit 【電學】程序電路。

【電學】程序電路。 “sequential“ 中文翻譯：   adj. 1.繼續的；連續的；隨著…而發生的 (to)。 ...“circuit“ 中文翻譯：   n. 1.(某一范圍的)周邊一圈；巡回，周游；巡回路線[ ...“asynchronous sequential circuit“ 中文翻譯：   異步時序電路“autonomous sequential circuit“ 中文翻譯：   自激時序電路“clocked sequential circuit“ 中文翻譯：   時鐘進序電路; 時鐘時序電路“complex sequential circuit“ 中文翻譯：   復式時序電路“flip-flop sequential circuit“ 中文翻譯：   觸發器時序電路“iterative sequential circuit“ 中文翻譯：   累接時序電路“linear sequential circuit“ 中文翻譯：   線性時序電路“pulse mode sequential circuit“ 中文翻譯：   脈沖式進序電路“sequential flasher circuit“ 中文翻譯：   順序閃光回路“sequential logic circuit“ 中文翻譯：   時序邏輯電路“sequential logical circuit“ 中文翻譯：   時序邏輯電路“sequential start circuit“ 中文翻譯：   程序起動電路“sequential switch circuit“ 中文翻譯：   時序開關電路“sequential switching circuit“ 中文翻譯：   依次轉換電路; 依次轉接電路“synchronous sequential circuit“ 中文翻譯：   同步時序電路“sequential“ 中文翻譯：   adj. 1.繼續的；連續的；隨著…而發生的 (to)。 2.結果的。 3.〔美俚〕(避孕丸)按期服食的。 n. 〔pl.〕 〔美俚〕按期服食的避孕丸。 adv. -ly “access sequential“ 中文翻譯：   序列存取“bit sequential“ 中文翻譯：   位序列的“chain, sequential“ 中文翻譯：   序列鏈路“construct, sequential“ 中文翻譯：   序列構造“control, sequential“ 中文翻譯：   順序控制“dot sequential“ 中文翻譯：   點順序制的“dot-sequential“ 中文翻譯：   adj. 【無線電】(彩色電視)點順序制的。

sequester

Some theoretical extensions are first made in this paper , with the following concepts , theorems and models presented - partial derivative and high - order partial derivative of waveform polynomial for describing the relation between input transitions and output transitions and redefining circuit sensitization ; the concept of waveform polynomial vector for describing a circuit with multiple inputs and outputs , especially for the unified description of circuit modules ; a sensitization theorem for sequential circuits for the purpose of exact timing ; theorems for transition numbers in circuits used to solve problems on noise , power consumption and etc ; waveform polynomial description for sequential circuits used to give a unified form for the function and timing behavior of a sequtial circuit ; and a data structure of generalized list for the representation and manipulation of waveform polynomial 波形多項式偏導和高階偏導的新概念，用來精確描述輸出跳變與輸入跳變之間的關系，并在本文中用來重新定義了電路的敏化和冒險；波形多項式向量的概念，用于形式化描述實際中的多輸入多輸出的電路，特別是用于統一描述電路模塊的功能及定時行為；時序電路的敏化定理，用于時序電路精確定時分析；波形多項式描述跳變及跳變數的定理，用于噪聲、功耗等問題的描述；時序電路的完整波形多項式描述，用于時序電路功能和定時行為的統一描述；波形多項式的多項式符號表示和運算的模型以及數據結構，用來實現對波形多項式比較有效的描述和運算。

Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed . compared with tranditional methods , it is not too optimistic or pessimistic , fit for the exact timing of high - speed circuit design 在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。

Flip - flop is the core of sequential circuits , this dissertation designed a synchronous set - reset edge - trigged jk flip - flop based on rt quantum devices , the jk flip - flop has strong function and high speed , and also riches the types of flip - flops in quantum circuits 所設計的jk觸發器功能強，且與傳統的觸發器相比，基于rt量子器件的邊沿型jk觸發器具有量子器件的功耗低、速度快、電路簡單等特點。本文設計的jk觸發器豐富了量子電路中觸發器的種類，使得量子時序電路的設計更為靈活。

We first propose and implement a sequential word - level pattern parallel fs algorithrn for synchionous sequential circuits . differing from other similar algorithins , it utilizes the relative independence of every fault test sequence generated by the g - f two - value tg algorithm , pwtitions and dynamically mounts test pattem , avoids redundant simulation for added synchlronous sequence , and gets better results 首先提出并實現了一個新的同步時序電路單機字級測試碼并行fs算法，該算法與現有同類方法的不同在于，利用確定性g - f二值tg算法的每個故障測試序列之間的相對獨立性，對測試碼進行分解并動態組裝，避免了對添加的同步序列的冗余模擬，效果較好。

Most of the circuit structures met in calendar schematic and the fundamental idea of analysis and design of the sequential circuit are discussed in this paper and the operation principle and the design method are analyzed from two points , one is the circuit theory of all the modules , the other is how the whole system works . the paper also expounds the design method - and the design flow of the 1c by the numbers through real examples 本文詳細討論了萬年歷電路分析與設計中遇到的各種電路類型和時序電路分析設計的基本思想，從萬年歷各子模塊的電路原理和整個系統如何運作兩個角度深入分析了萬年歷電路的工作原理和設計思路，以實例系統地闡述了集成電路的設計方法與設計流程。

Test vector generation based on ant algorithm is presented and implemented , the pheromone computation formula for sequential circuits and status transfer rules are given , and the test results are compared with the results of the other existing test generators - hitec , gatest , cris , digate and strategate , based on standard sequential circuits iscas ' 89 and other synchronous sequential circuits 提出并實現了基于螞蟻算法的測試矢量生成，給出了針對時序電路測試矢量生成的信息素計算公式和狀態轉移規則。在iscas ’ 89標準時序電路和幾個同步時序電路上實現了測試生成，并將生成結果和其它現有測試生成器( hitec ， gatest ， cris ， digate ， strategate )的生成結果作了比較、分析。

To compensate the shortage of the bigger test set of pure ant algorithm , the method of crossing ant algorithm and genetic algorithm is presented . meanwhile , the implementation methods of the objective function , selection operator , crossover operator , and mutation operator are given , and the test results are compared with the results of ant algorithm , based on standard sequential circuits iscas ' 89 為彌補單純采用螞蟻算法進行測試矢量生成時，測試矢量集過大的缺點，摘要提出了螞蟻算法和遺傳算法交叉的測試生成方法，給出了遺傳算法的目標函數、選擇算子、交叉算子、變異算子的實現方法。

Internal scan is advanced for the difficulty of fixing the state of sequential circuit , can be divided into full - scan and partial - scan . in this paper we use full - scan according to the real circumstance of estarl and get high fault coverage with very little impact on the circuit 本文根據estar1的實際情況，設計實現了全掃描結構，既得到了較高的故障覆蓋率，又對電路的延遲和芯片面積影響很小(延遲時間增加0 . 3 ，芯片面積增加0 . 01 ) 。

According to the redundancy in digital circuits , we investigate the diversified redundancy - restraining techniques for lower - power cmos circuits . to erase the redundant transition of the clock , the logic design of double - edge - triggered flip - flop is presented and applied in sequential circuit design 為消除時鐘信號的兀余跳變，提出了利用時鐘兩個方向跳變的雙邊沿觸發器邏輯發計并應用于時序電路設計中。

Due to the parallel global optimization characteristics of the genetic algorithm , the crossover using ant algorithm and genetic algorithm is adapted to generate the initialization vector of the sequential circuit , for avoiding the local optimization of ant algorithm 此外，為避免螞蟻算法陷于局部最優，利用遺傳算法具有并行全局尋優特點，將遺傳算法與螞蟻算法的交叉算法引入時序電路初始化矢量生成。

Model - checking is one of the most successful automatic verification techniques in the past two decades . it has been used in the analysis and verification of finite - state systems such as sequential circuit designs and communication protocols 模型檢測技術是近二十年來最成功的自動驗證技術之一，目前被廣泛的應用于有窮狀態系統(包括電路設計和通訊協議等)的分析與驗證。

The basic principle of ant algorithm is discussed , ant algorithm for sequential circuits initialization is presented , and the pheromone computation formula for sequential circuits initialization and status transfer rules are given 根據螞蟻算法的基本原理，提出了基于螞蟻算法的時序電路初始化方法，給出了針對時序電路初始化的信息素計算公式和狀態轉移規則。

As emphasis , we propose a new backward width - flrst search circuit partitioning method with flip - flop as core for synchronous sequential circuits . and then based on it , we develop a new circuit parallel tg algorithm 最后重點對電路并行方法進行了研究，提出了一種新的以觸發器為核且消除大功能塊之間反饋的寬度優先反向搜索同步時序電路劃分方法。

Base on the existing synchronous sequential circuits fault simulator - hope , the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly 本文在同步時序電路故障模擬器? hope的基礎上，率先對基于螞蟻算法的時序電路測試矢量生成方法作了系統的開拓性研究。

To avoid the idleness state and the corresponding power dissipation in sequential circuits , a clock gating technique and a multi - code assignment using redundant state is adanced to reduce power dissipation 為抑制時序電路中的冗余現象，研究了時序電路的門控時鐘技術，并利用t型觸發器進行時序電路設計。

In order to eliminate the sequence conflict of synchronous sequential circuit and shorten the designable time of integrated circuits , the algorithms of retiming is deeply researched in this paper 本文對重定時算法進行了深入研究，目的在于消除同步時序電路的時序沖突，從而縮短集成電路的設計時間。

The automatic test vector generation method based on fault simulation is described , and the whole procedure of atpg of sequential circuits is analyzed , fault simulator - hope as an example 本文闡述了基于模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。

The international standard sequential circuits iscas ' 89 ( addendum ' 93 included ) is used to verify the algorithm , and the results are better than other algorithms “ 采用國際標準時序電路iscas ’ 89 (包括addendum ’ 93 )進行了算法驗證，取得了優于文獻中其它算法的結果。

The sy - stem had different requirements on time sequence in high - speed clock and low - speed clock situations , which resulted in the complexity of the sequential circuit 在高速時鐘和低速時鐘的情況下，系統有不同的時序要求，這就決定了時序電路的復雜性。